The present invention relates to a semiconductor device having a MISFET and, more particularly, to a semiconductor device having a structure in which part of the source/drain regions is formed above the interface between the substrate and the gate insulating film.
MISFETs suffer a phenomenon, i.e., so-called DIBL (Drain Induced Barrier Lowering) that the threshold voltage drops upon application of the drain voltage. This will be briefly explained using an n-type MISFET in FIG. 1A.
In FIG. 1A, a polysilicon gate electrode 1 doped with B, As, or P is formed via a gate insulating film 2 made of a silicon oxide film on an Si semiconductor layer 7 for forming a channel region. Source and drain regions 3 and 4 of a conductivity type opposite to that of the semiconductor layer 7 are formed on the two sides of the gate electrode 1 by ion-implanting P or As. Insulating films 8 are formed on the two sides of the gate electrode 1, whereas an insulating film 8' is formed on top of the gate electrode 1.
Assume that the drain region 4 receives a higher voltage than that for the source region 3. This is the case wherein the n-type MISFET is used to form, e.g., a logic circuit for a static inverter in FIG. 1B. In FIG. 1B, the gate electrode of an n-type MISFET 9 is connected to the gate electrode of a p-type MISFET 9' to form an input electrode 10 of the inverter. The drain 4 of the n-type MISFET 9 is connected to the drain 4 of the p-type MISFET 9' to form an output 10' of the inverter. The source 3 of the n-type MISFET 9 is grounded (0V), and the source of the p-type MISFET 9' is connected to a power supply terminal (V.sub.DD). In this manner, a static inverter is constructed.
When a logic circuit is formed using an n-type MISFET, like this inverter, the voltage applied to the p-n junction between the drain and the substrate is higher than the voltage applied to the p-n junction between the source and the substrate. For this reason, as shown in FIG. 1A, a substrate-side edge 5' of a depletion layer formed by the p-n junction between the drain and the substrate extends to the semiconductor layer 7 much more than a substrate-side edge 5" of the depletion layer defined by the p-n junction between the source and the substrate. That region (charge share region) 6 of the depletion layer, which is below the gate electrode and shared by a drain depletion layer, widens when the drain voltage increases. As a result, the depletion layer that can be controlled by the gate narrows. As the negative charges contained in the gate-controlled depletion layer decrease, the threshold voltage of the transistor lowers. Accordingly, the threshold voltage drops upon application of the drain voltage.
This phenomenon is so-called DIBL. Since the ratio of the charge share region 6 to the overall depletion layer below the gate electrode increases with a decrease in gate length, the drop in threshold voltage becomes prominent as the gate length becomes shorter.
To suppress widening of the charge share region upon application of the drain voltage, it has been found effective to extend the depletion layer to the drain region upon application of the drain voltage and as a result, suppress substrate-side widening of the depletion layer formed in the semiconductor layer 7. However, when this method is adopted in a simple drain structure in which the drain is formed nearer the substrate than the interface between the substrate and the gate insulating film, the parasitic resistance of the drain increases undesirably. This will be explained using a uniformly doped drain structure in FIGS. 2A and 2B.
FIG. 2A is an enlarged sectional view showing the drain and the substrate when voltages V.sub.BS and V.sub.D are respectively applied to the substrate electrode and the drain. Donors are uniformly doped in the drain region 4 at an impurity concentration N.sub.D, and acceptors are uniformly doped in the semiconductor layer 7 at an impurity concentration N.sub.A. In this case, using depletion approximation with reference to a charge distribution shown in FIG. 2B corresponding to the section taken along the line A-A' in FIG. 2A, a distance X.sub.n from the boundary between the drain region 4 and the semiconductor layer 7 to the edge of the depletion layer extending to the drain region is given by: EQU X.sub.n ={2.epsilon..sub.S (V.sub.D +V.sub.BI -V.sub.BS)/q}.sup.0.5.times.{N.sub.A /N.sub.D /(N.sub.A +N.sub.D)}.sup.0.5 (1)
where .epsilon..sub.S is the dielectric constant of the semiconductor, and q is the elementary charge, V.sub.BI is the built-in voltage.
From equation (1), X.sub.n monotonically decreases with increasing N.sub.D. The upper limit of the impurity amount which can be doped to the semiconductor is determined by the solid solubility limit. Letting N.sub.Dmax be the upper limit of the donor impurity amount, the lower limit X.sub.nmin of X.sub.n is given from equation (1) by: EQU X.sub.nmin ={2.epsilon..sub.S (V.sub.D +V.sub.BI -V.sub.BS)/q}.sup.0.5.times.{N.sub.A /N.sub.Dmax /(N.sub.A +N.sub.Dmax)}.sup.0.5 (2)
Further, when y represents the drain length, W represents the channel width, X.sub.j represents the formation depth of the drain region in FIG. 2A, and .rho. represents the resistivity, the resistance R of the drain is
R=y.rho./{W(X.sub.j -X.sub.n)} (3)
Since .rho. monotonically increases with N.sub.D, the relation of R for X.sub.n shown in FIG. 3 can be obtained using equations (2) and (3). From equation (2), as X.sub.n comes closer to X.sub.j, R diverges infinitely. That is, when X.sub.n is increased to suppress widening of the charge share region by extending the depletion layer to the drain region, the resistance of the drain increases infinitely if X.sub.j remains constant. From equation (2), since X.sub.nmin is a constant that is determined regardless of X.sub.j, the allowable range of X.sub.n narrows with decreasing X.sub.j. If X.sub.n varies due to variations in impurity concentration and defect distribution, the parasitic resistance of the drain also varies. Consequently, the drivability varies between devices, and thus the delay time of the logic circuit varies, which makes it difficult to design a high-speed optimum operation.
According to the study made by the present inventors, such an increase in parasitic resistance can be effectively prevented by a so-called elevated (to be referred to as EV hereinafter) source/drain structure like the one shown in FIG. 4A in which at least part of the source/drain regions is formed above the interface between the substrate and the gate insulating film. This EV source/drain structure itself is described in, e.g., S. Nishimatsu, Y. Kawamoto, H. Masuda, R. Hori, and O. Minato, "Grooved Gate MOSFET", Jpn, J. Appl. Phys., 16; Suppl. 16-1, 179 (1977).
The structure in FIG. 4A is basically the same as that in FIG. 1A except that the source and drain regions 3 and 4 are formed above the interface between the semiconductor layer 7 and the gate insulating film 2. A source contact formation region 3' and a drain contact formation region 4' are respectively formed X.sub.1 apart from gate insulating film 2' in the source region 3 and the drain region 4. The broken lines in FIG. 4A indicate the edges of a depletion layer formed in the source and drain regions 3 and 4 and the semiconductor layer 7. The thickness of the gate insulating film 2 between the gate electrode 1 and the semiconductor layer 7 is equal to or smaller than the thickness of a gate insulating film 2' between the gate electrode 1 and the source region 3.
In the EV source/drain structure, letting y be the distance from the upper surface of the doped drain layer to the depletion layer, W be the channel width, X.sub.1 be the length of the drain region 4 measured from the drain contact region 4', and .rho. be the resistivity, as shown in FIG. 4A, the parasitic resistance R from the upper edge of the drain to an edge 11 of the depletion layer in the drain region is EQU R=.rho.X.sub.1 /(Wy) (4)
From equation (4), unlike equation (3), the resistance R per unit width W can be reduced by increasing the height y of the drain region 4 or decreasing X.sub.1. This resistance R is not a function of the depth X.sub.j of the source/drain regions 3 formed in the semiconductor layer 7, and thus can be kept small even if X.sub.j is decreased to almost 0 nm.
In the conventional EV source/drain structure in FIG. 4A, the impurity concentration of the source/drain is constant or increases upward in the gate stacking direction from the substrate to the interface of the depletion layer. In this EV source/drain structure, if X.sub.n is increased to reduce the charge share, the current drivability structurally greatly lowers.
In FIG. 4A, the voltage V.sub.BS, the voltage V.sub.D, and 0V are respectively applied to a substrate electrode, the drain region 4, and the source region 3. Donors are uniformly added to the source and drain regions 3 and 4 at an impurity concentration N.sub.D, and acceptors are uniformly added to the semiconductor layer 7 at an impurity concentration N.sub.A. In this case, the distance X.sub.n from the boundary between the drain region 4 and the semiconductor layer 7 to the edge of the depletion layer extending to the drain region can be given using depletion approximation by: EQU X.sub.n ={2.epsilon..sub.S (V.sub.D +V.sub.BI -V.sub.BS)/q}.sup.0.5.times.{N.sub.A /N.sub.D /(N.sub.A +N.sub.D)}.sup.0.5 EQU dX.sub.n /dV.sub.D =.epsilon..sub.S /q.multidot.{2.epsilon..sub.S (V.sub.D +V.sub.BI -V.sub.BS)/q}.sup.-0.5.times.{N.sub.A /N.sub.D /(N.sub.A +N.sub.D)}.sup.0.5 (5)
From equation (5), the rate of change of X.sub.n with respect to V.sub.D decreases with increasing V.sub.D. The change amount of X.sub.n at a drain voltage in the neighborhood of 0V is larger than the change amount of X.sub.n at a higher drain voltage.
This feature becomes more noticeable in a structure in which the impurity concentration of the source/drain increases upward in the gate stacking direction from the substrate to the interface of the depletion layer. In this structure, N.sub.D in equation (5) is effectively higher for higher V.sub.D than for lower V.sub.D. As described with reference to equation (3), if X.sub.n varies due to variations in impurity concentration and defect distribution, the parasitic resistance of the drain also varies, and the drivability varies between devices, which makes it difficult to design a high-speed optimum operation.
Further, the source region generally has the same structure as that of the drain region. In this case, a distance X.sub.n ' from the boundary between the source region 3 and the semiconductor layer 7 to the edge of the depletion layer extending to the source region can be given using depletion approximation by: EQU X.sub.n '={V.sub.BI -V.sub.BS }/(V.sub.D +V.sub.BI -V.sub.BS)}.sup.0.5 X.sub.n (6)
From equation (6), X.sub.n ' is proportional to X.sub.n.
When, therefore, the source region has the same structure as that of the drain region, if X.sub.n is increased to reduce the charge share of the drain region, the width X.sub.n ' of the depletion layer at the source edge inevitably increases. From equation (6), when the voltage of the drain region is higher than the voltage of the source region, the change amount of the source region X.sub.n ' with the source voltage is larger than the change amount of the drain region X.sub.n with the drain voltage. At a source voltage of approximately 0V, the position of the edge of the depletion layer in the source region greatly changes depending on the source voltage.
For example, in a static NAND logic circuit shown in FIG. 4B, when the source region of the n-type MISFET 9 is connected to the drain region of another n-type MISFET 9, the source voltage of the transistor series-connected to the source region 3 side rises owing to the drain/source resistance and channel resistance of the transistor. As a result, the width X.sub.n ' of the depletion layer increases, and an edge 12 of the depletion layer which actually serves as the edge of the source region in FIG. 4A recedes from the interface between the gate insulating film 2 and the semiconductor layer 7. For this reason, the charge amount injected from the source edge decreases to lower the current drivability.
Particularly in the EV source/drain structure like the one in FIG. 4A in which the source/drain regions are formed above the interface between the substrate and the gate insulating film, since the source-region-side edge 12 of the depletion layer is formed above the interface between the semiconductor layer 7 and the gate insulating film 2, the current drivability remarkably lowers. This is because a so-called edge effect inhibits electric field from reaching the portions near the corners defined by the bottom and side surfaces of the gate electrode 1, and an inversion layer is hard to form at the corners.
As described above, in the MISFET structure in FIG. 1A, the drain voltage dependence of the threshold voltage due to DIBL cannot be reduced, and stable current drivability cannot be maintained by keeping the parasitic resistance of the source region small. In the EV source/drain structure in FIG. 4A, the current drivability lowers upon an increase in source voltage.